Advanced process flow for quantum memory devices and josephson junctions with heterogeneous integration

US9455391B1 · kind B1 · utility

Assignee

• The United States of America, as represented by Secretary of the Navy · US

Inventors

• Osama M. Nayfeh · San Diego, US
• Son Dinh · San Diego, US
• Anna Leese de Escobar · Encinitas, US
• Kenneth Simonsen · San Diego, US

Key dates

• Filing date: Mar 3, 2016
• Grant date: Sep 27, 2016
• Expiry date: Mar 3, 2036

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10N69/00
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

A process for constructing a superconducting Josephson-based nonvolatile quantum memory device comprising: sequentially depositing on a silicon substrate a thermal oxide buffer layer, a superconductor bottom-electrode thin film, and an oxide isolation layer; patterning an active window having dimensions smaller that 10 nanometers in the oxide isolation layer; then sequentially depositing a bottom tunnel oxide layer, a charge-trapping layer, a top cap, and a top superconductor electrode layer; defining an active region by dry etching down to the oxide isolation layer while protecting the active region from etch chemistry; depositing a device passivation layer; defining and patterning vias from a top of the device passivation layer to the superconductor bottom-electrode thin film and to the top superconductor electrode of the active region; and depositing metal interconnect into the vias.