Scalable periphery for digital power control
US9455670B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 23, 2013 |
| Grant date | Sep 27, 2016 |
| Priority date | — |
| Expiry date | Oct 17, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2203/7236
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A scalable periphery digital power control arrangement is presented. The scalable periphery digital power control arrangement comprises a plurality of PMOS transistors connected in parallel, where the plurality of transistors is operatively coupled to a voltage source. The plurality of PMOS transistors that is operatively coupled to the voltage source can operate as a controlled current source. Current flow from the voltage source can be controlled by a logic circuit, which sends a logic signal to enable or disable each individual PMOS transistor of the plurality of PMOS transistors connected in parallel. As more PMOS transistors are enabled, the current flow through the scalable periphery digital power control arrangement to the amplifier can increase.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.