Clock enabling circuit

US9455710B2 · kind B2 · utility

Assignee

• Dialog Semiconductor (UK) Limited · GB

Inventors

• Joachim Riexinger · Bad Boll, DE
• Armin Fischer · Munich, DE

Key dates

• Filing date: Sep 19, 2014
• Grant date: Sep 27, 2016
• Expiry date: Dec 20, 2034

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F1/3237
• WIPO field: Basic communication processes
• WIPO sector: Electrical engineering

Abstract

A clock enabling circuit for providing a gated clock signal in response to receiving clock request information is presented. The clock enabling circuit comprises a clock request input, a clock input, and a flip-flop stage. It also includes a first sub-circuitry comprising a first input being coupled with the clock request input and an output being coupled with the flip-flop stage for providing a set information to the flip-flop stage in response to the receipt of the clock request information, the flip-flop stage being configured to provide a clock enabling information in response to receiving the set information and a second sub-circuitry comprising a first and a second input, the first input being coupled with the clock input and the second input being coupled with the flip-flop stage, the second sub-circuitry comprising an output for providing the gated clock signal in response to receiving the clock enabling information.