Patent · US Active

Digital counter comprising reduced transition density

US9455717B2 · kind B2 · utility

1Cited by
13References
23Claims
0Family size

Assignee

Inventor

Key dates

Filing dateAug 7, 2014
Grant dateSep 27, 2016
Priority date
Expiry dateDec 20, 2034

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH03K23/588
  • WIPO fieldBasic communication processes
  • WIPO sectorElectrical engineering

Abstract

The present document relates to a digital counter providing counting information comprising at least a first and a second counting module, said counting modules being serially coupled forming a counting module chain; each counting module comprising at least a first and a second digital storage cell, each counting module providing module counting information comprising a width of at least two bits; the counting modules being adapted to change only one bit of said module counting information between two successive counting states; wherein the counting modules are coupled such that the start of counting of the second counting module is triggered by the first counting module if said first counting module once has passed through its possible counting states.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.