Method and apparatus for fast locking of a clock generating circuit
US9455722B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 30, 2005 |
| Grant date | Sep 27, 2016 |
| Priority date | — |
| Expiry date | Jun 27, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/10
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
In a method and apparatus for using a clock generating circuit to minimize settling time after dynamic power supply voltage ramping, a clock signal may be generated using a clock generating circuit having, among other things, open feedback loop switch logic and a dynamic fast lock control signal generator. Whereupon, when in operation, the open feedback loop switch logic is responsive to a controlled change in power supply voltage condition such that a feedback loop of the clock generating circuit is opened during power supply voltage ramping (e.g., during transitions to or from battery conservation modes). In response to opening the feedback loop, the dynamic fast lock control signal generator selectively applies a stabilizing control signal to a variable clock signal generator (e.g., a voltage controlled oscillator) such that the generated clock signal can quickly lock onto the proper target frequency.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.