Method and apparatus for avoiding spurs in chip
US9455729B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 15, 2014 |
| Grant date | Sep 27, 2016 |
| Priority date | — |
| Expiry date | Sep 15, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04B15/04
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method is for rejecting spurs within a chip containing analog and digital functions. The spurs may be timed by a clock signal derived from the output frequency of a high frequency phase locked loop. Original analog rejection bandwidths associated with operation of analog functions may be determined, and then original spurs associated with operation of the digital functions and capable of directly or indirectly affecting the original analog rejection bandwidths may be identified. A final analog rejection bandwidth may be determined based on the original analog rejection bandwidths, and final spurs may be obtained based on the original spurs. A frequency shift of the output frequency of the high frequency phase locked loop to effectuate a rejection of the final spurs from the final analog rejection bandwidth may be determined, and the high frequency phase locked loop may be controlled to shift the output frequency by the frequency shift.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.