Delta-sigma analog-to-digital converter (ADC) with time-interleaved (TI) or two-step successive approximation register (SAR) quantizer
US9455737B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 22, 2016 |
| Grant date | Sep 27, 2016 |
| Priority date | — |
| Expiry date | Feb 22, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M3/47
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Certain aspects of the present disclosure provide a delta-sigma modulator (DSM) using time-interleaved (TI) successive approximation register (SAR) analog-to-digital converters (ADCs). For example, two SAR ADCs may be configured to alternately sample and process an input signal and provide a feedback signal for the DSM using excess loop delay (ELD). In other aspects, the DSM may be implemented using a two-step SAR quantizer. For example, a first SAR ADC may sample an input signal to generate a most-significant bit (MSB) portion of an output of the DSM, while the second SAR ADC may subsequently sample a residue from the first SAR ADC conversion and generate a least-significant bit (LSB) portion of the output of the DSM. With these techniques, higher bandwidths may be obtained in high accuracy delta-sigma ADCs without using increased sampling rates.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.