Tray for aligning semiconductor packages and test handler using the same, and method of aligning semiconductor packages and test method using the same
US9459315B2 · kind B2 · utility
1Cited by
1References
24Claims
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Key dates
| Filing date | Mar 18, 2014 |
| Grant date | Oct 4, 2016 |
| Priority date | — |
| Expiry date | Nov 29, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/68
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A tray for aligning semiconductor packages, a test handler using the same, a method of aligning the semiconductor packages, and a test method using the same include a tray main body comprising a plurality of package pocket portions at which a plurality of semiconductor packages are individually received and an air position-aligning unit coupled to the tray main body. The air position-aligning unit applies air having a preset pressure to the semiconductor package received at the package pocket portion. The semiconductor package is aligned at the package pocket portion.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.