System and method for zero contention memory bank access in a reorder stage in mixed radix discrete fourier transform
US9459812B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 3, 2015 |
| Grant date | Oct 4, 2016 |
| Priority date | — |
| Expiry date | Feb 3, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Device and method for writing Discrete Fourier transform (DFT) samples in a memory in a reorder stage, the memory includes memory banks, each having a dedicated address generator. The method includes: dividing the DFT samples into R(reorder) equally sized segments, where R(reorder) is the radix value of the reorder stage of the DFT; checking whether a number of butterfly computations per cycle of a reorder stage of the DFT operation times R(reorder), denoted as P, is not larger than the number of segments; if P is larger than the number of segments: further dividing the segments or sub-segments into X equally sized sub-segments, where X is a radix value of a next stage of the DFT operation until P is not larger than the number of sub-segments; and mapping the sub-segments to the memory, each in a separate row, with an offset that includes segment offset and sub-segment offset.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.