Data decoder with trapping set flip bit mapper
US9459956B2 · kind B2 · utility
12Cited by
15References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 2, 2013 |
| Grant date | Oct 4, 2016 |
| Priority date | — |
| Expiry date | May 7, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/1105
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A low density parity check decoder includes a variable node processor operable to generate variable node to check node messages and to calculate perceived values based on check node to variable node messages, a check node processor operable to generate the check node to variable node message vectors and to calculate checksums based on the variable node to check node messages, and a convergence detector and bit map generator operable to convergence of the perceived values and to generate at least one bit map that identifies variable nodes that are connected to check nodes with unsatisfied parity checks.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.