Patent · US Active

System, method, and computer program product for input/output buffer modeling

US9460250B1 · kind B1 · utility

1Cited by

6References

15Claims

0Family size

Assignee

Cadence Design Systems, Inc. · US

Inventors

Jose Schutt-Aine · Savoy, US
Dennis C. Nagle · Baltimore, US
Feras Al-Hawari · Chelmsford, US
Ambrish Kant Varma · Chelmsford, US
Jilin Tan · Nashua, US
Ping Liu · Shanghai, CN
Shangli Wu · Harrison, US
Yubao Meng · Hubei, CN
Qi Zhao · Chongqing, CN
Zhongyong Zhou · Shanghai, CN

Key dates

Filing date	Jul 30, 2012
Grant date	Oct 4, 2016
Priority date	—
Expiry date	Mar 19, 2034

Classification

Technology area (CPC G)Physics
CPC primaryG06F2119/12
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

The present disclosure relates to a computer-implemented method for transient simulation of an input/output buffer model. The method may include generating an input/output buffer data file associated with a first model of an electrical circuit. The method may also include determining at least one of a node voltage and a branch current associated with the electrical circuit using, at least in part, a latency insertion method, the method may further include performing one or more simulations on a second model of an electrical circuit, the one or more simulations incorporating, at least in part, the input/output buffer data file and the latency insertion method.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.