Semiconductor device manufacturing method
US9460927B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 22, 2015 |
| Grant date | Oct 4, 2016 |
| Priority date | — |
| Expiry date | Jun 22, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/112
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device manufacturing method for a semiconductor device having a p-n junction formed of a first conductivity type first semiconductor region and a second conductivity type second semiconductor region, and comprising a low-lifetime region that has a carrier lifetime shorter than that in other regions at the interface of the p-n junction. The method includes an implantation process of, after implanting a second conductivity type impurity into the surface of the first semiconductor region with a first acceleration energy, implanting a second conductivity type impurity, with a second acceleration energy differing from the first acceleration energy, into the surface of the first semiconductor region into which the second conductivity type impurity has been implanted.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.