Meander line resistor structure
US9461048B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 12, 2015 |
| Grant date | Oct 4, 2016 |
| Priority date | — |
| Expiry date | Oct 12, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/209
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A system comprises a first transistor comprising a first drain/source region and a second drain/source region, a second transistor comprising a third drain/source region and a fourth drain/source region, wherein the first transistor and the second transistor are separated by an isolation region, a first resistor formed by at least two vias, wherein a bottom via of the first resistor is in direct contact with the first drain/source region, a second resistor formed by at least two vias, wherein a bottom via of the second resistor is in direct contact with the second drain/source region, a bit line connected to the third drain/source region through a plurality of bit line contacts and a capacitor connected to the fourth drain/source region through a capacitor contact.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.