Vertical memory devices and methods of manufacturing the same
US9461061B2 · kind B2 · utility
4Cited by
2References
17Claims
0Family size
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Key dates
| Filing date | Nov 18, 2014 |
| Grant date | Oct 4, 2016 |
| Priority date | — |
| Expiry date | Nov 18, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/693
Abstract
A method of manufacturing a vertical memory device includes forming alternating and repeating insulating interlayers and sacrificial layers on a substrate, the sacrificial layers including polysilicon or amorphous silicon, forming channel holes through the insulating interlayers and the sacrificial layers, forming channels in the channel holes, etching portions of the insulating interlayers and the sacrificial layers between adjacent channels to form openings, removing the sacrificial layers to form gaps between the insulating interlayers, and forming gate lines in the gaps.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.