Array substrate, manufacturing method for the same, display device and electronic product
US9461078B1 · kind B1 · utility
Assignees
Inventors
Key dates
| Filing date | Apr 8, 2014 |
| Grant date | Oct 4, 2016 |
| Priority date | — |
| Expiry date | Sep 2, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG02F1/136295
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
According to the method for manufacturing an array substrate of the present disclosure, when two non-adjacent conductive layers are electrically connected to each other through the via-holes, the insulating layers between the adjacent conductive layers may be etched by several etching processes so as to form the corresponding via-holes in the insulating layer, thereby to achieve the electrical connection between the non-adjacent conductive layers. Meanwhile, it is also able to achieve the electrical connection between the adjacent conductive layers through the via-holes in each etching process. In other words, when at least three conductive layers are electrically connected with each other through the via-holes, merely the insulating layer between the adjacent conductive layers is etched in each etching process.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.