Gate-drive-on-array circuit for use with oxide semiconductor thin-film transistors
US9461627B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 5, 2014 |
| Grant date | Oct 4, 2016 |
| Priority date | — |
| Expiry date | Jan 30, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2300/0842
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A gate-drive-on-array circuit for use with oxide semiconductor thin-film transistors of the present invention uses two constant-voltage negative potential sources (VSS1, VSS2) that are reduced step by step and low potentials of a high-frequency clock signal (CK(n)) and a low-frequency clock signal (LC1, LC2) to ensure an up-pull circuit portion (200) is maintained in a well closed condition during a non-operating period without being affected by the high-frequency clock signal (CK(n)) so as to ensure the circuit operates normally. Further, the first down-pull circuit portion (400) is re-designed to prevent influence thereof imposed on the outputs of the first node (Q(N)) and the output terminal (G(N)) so as to ensure the first node (Q(N)) and the output terminal (G(N)) can supply the outputs normally without generating signal distortion.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.