Digitally-corrected analog-to-digital converters
US9461660B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 11, 2015 |
| Grant date | Oct 4, 2016 |
| Priority date | — |
| Expiry date | Nov 11, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/60
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for a digitally-corrected analog-to-digital converter (ADC) are disclosed. The apparatus comprises a nonlinearity generator that generates one or more nonlinear characteristics of a time varying input signal and that causes unwanted signal components at frequencies other than a frequency of the time varying input signal, a frequency response modifier coupled to the nonlinearity generator that modifies the unwanted signal components by altering an amplitude of the unwanted signal components, a frequency response compensator coupled to the frequency response modifier, wherein the frequency response compensator compensates for the modification introduced by the frequency response modifier to provide a filtered digital signal, and an inverse nonlinearity generator coupled to the frequency response compensator for receiving the filtered digital signal, wherein the inverse nonlinearity generator compensates for the one or more nonlinear characteristics.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.