Patent · US Active

Orthogonal differential vector signaling codes with embedded clock

US9461862B2 · kind B2 · utility

89Cited by

121References

19Claims

0Family size

Assignee

Kandou Labs SA · CH

Inventors

Brian Holden · Monte Sereno, US
Amin Shokrollahi · Préverenges, CH

Key dates

Filing date	Aug 3, 2015
Grant date	Oct 4, 2016
Priority date	—
Expiry date	Aug 3, 2035

Classification

Technology area (CPC Y)Emerging Cross-Sectional Technologies
CPC primaryY02D10/00
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Orthogonal differential vector signaling codes are described which support encoded sub-channels allowing transport of distinct but temporally aligned data and clocking signals over the same transport medium. Embodiments providing enhanced LPDDR interfaces are described which are suitable for implementation in both conventional high-speed CMOS and DRAM integrated circuit processes.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.