Partitioned switch mode power supply (SMPS) interface
US9465421B2 · kind B2 · utility
1Cited by
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23Claims
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Key dates
| Filing date | Jun 24, 2013 |
| Grant date | Oct 11, 2016 |
| Priority date | — |
| Expiry date | Jun 28, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH02M3/157
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A single-wire interface of an application processor that communicates with another single-wire interface of a power management unit (PMU) via a control signal line. The control signal line can be a single signal path. Further, the single-wire interfaces can communicate with each other only via the control signal line. The single-wire interfaces can be utilized for the communication of pulse width modulation (PWM) control signals, current sensing, and Zero-I detection.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.