FFMA operations using a multi-step approach to data shifting
US9465575B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 5, 2013 |
| Grant date | Oct 11, 2016 |
| Priority date | — |
| Expiry date | Jun 9, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/483
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A fused floating-point multiply-add element includes a multiplier that generates a product, and a shifter that shifts an addend within a narrow range. Interpreting logic analyzes the magnitude of the addend relative to the product and then causes logic arrays to position the shifted addend within the left, center, or right portions of a composite register depending in the magnitude of the addend relative to the product. The interpreting logic also forces other portions of the composite register to zero. When the addend is zero, the interpreting logic forces all portions of the composite register to zero. Final combining logic then adds the contents of the composite register to the product.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.