Variable-latency speculating pipelined booth multiplier with statistical carry estimation for error detection and recovery
US9465579B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 11, 2014 |
| Grant date | Oct 11, 2016 |
| Priority date | — |
| Expiry date | Jan 2, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/533
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Provided is a method for processing pipelined data using a variable-latency speculating booth multiplier (VLSBM), including a first operation and a second operation. The first operation has the steps of partitioning partial products into a least significant part (LSP) and a most significant part (MSP), estimating a carry of the LSP, computing the MSP based on the estimated carry, computing the LSP independently to obtain a true carry and detecting a computation error by comparing the estimated carry with the true carry. Also, the second operation has the step of correcting the computation error based on the difference between the estimated carry and the true carry. Further, a VLSBM for processing pipelined data is also provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.