NUMA scheduling using inter-vCPU memory access estimation
US9465669B2 · kind B2 · utility
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25Claims
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Key dates
| Filing date | Mar 7, 2014 |
| Grant date | Oct 11, 2016 |
| Priority date | — |
| Expiry date | Sep 5, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/62
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a system having non-uniform memory access architecture, with a plurality of nodes, memory access by entities such as virtual CPUs is estimated by invalidating a selected sub-set of memory units, and then detecting and compiling access statistics, for example by counting the page faults that arise when any virtual CPU accesses an invalidated memory unit. The entities, or pairs of entities, may then be migrated or otherwise co-located on the node for which they have greatest memory locality.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.