Assessment of a high performance computing application in relation to network latency due to the chosen interconnects
US9465712B2 · kind B2 · utility
1Cited by
8References
17Claims
0Family size
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Key dates
| Filing date | Jun 26, 2013 |
| Grant date | Oct 11, 2016 |
| Priority date | — |
| Expiry date | Jul 20, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/3461
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and computer program product for testing a high performance computing application performing a computation within a clustered computer arrangement is disclosed. The high performance computing arrangement performances computations across processors in parallel wherein the processors cooperate to perform the computation. The application can be tested by adding delay and therefore latency to one or more commands inside of the precompiled application. The addition of delay can be used to simulate the performance of different interconnects that are used within the high performance computing arrangement.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.