Memory controller adaptable to multiple memory devices
US9465728B2 · kind B2 · utility
4Cited by
32References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 3, 2010 |
| Grant date | Oct 11, 2016 |
| Priority date | — |
| Expiry date | Aug 1, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/1694
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory controller, in one embodiment, includes a command translation data structure, a front end and a back end. The command translation data structure maps command operations to primitives, wherein the primitives are decomposed from command operations determined for one or more memory devices. The front end receives command operations from a processing unit and translates each command operation to a set of one or more corresponding primitives using the command translation data structure. The back end outputs the set of one or more corresponding primitives for each received command operation to a given memory device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.