Configurable interconnection system
US9465756B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 22, 2010 |
| Grant date | Oct 11, 2016 |
| Priority date | — |
| Expiry date | Apr 2, 2034 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An interconnection system, apparatus and method is described where the motherboard may be populated with less than all of the modules that it has been designed to accept while maintaining a configuration such that in the event of a module failure, a memory controller failure, or a combination thereof, the connectivity of the remaining modules is maintained. Where data is stored using a RAID organization of the memory on the modules, the data may be reconstructed to a spare module. The system also provides for the orderly incremental expansion of the memory by adding additional memory modules and memory controllers, while maintaining the connectivity properties.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.