Stretch dummy cell insertion in finFET process
US9465901B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 15, 2015 |
| Grant date | Oct 11, 2016 |
| Priority date | — |
| Expiry date | Jun 15, 2035 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02P90/02
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method embodiment includes identifying, by a processor, an empty region in an integrated circuit (IC) layout, wherein the empty region is a region not including any active fins. The method further includes providing a standard dummy fin cell and forming an expanded dummy fin cell. The standard dummy fin cell includes a plurality of partitions. The expanded dummy fin cell is larger than the standard dummy fin cell, and the expanded dummy fin cell includes integer multiples of each of the plurality of partitions. The empty region is filled with a plurality of dummy fin cells, wherein the plurality of dummy fin cells includes the expanded dummy fin cell. The plurality of dummy fin cells is implemented in an IC.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.