TFT array substrate, display panel and display device
US9466235B2 · kind B2 · utility
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19Claims
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Key dates
| Filing date | Jan 29, 2015 |
| Grant date | Oct 11, 2016 |
| Priority date | — |
| Expiry date | Jun 28, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2380/14
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A TFT array substrate is disclosed. The array substrate includes gate lines, first and second gate driving circuits, first, second, third, and fourth clock signal lines, first and second initial signal lines, first and second initial transistors, and first, second, third, and fourth clock transistors. The first gate driving circuit includes m stages of first repeating units. The second gate driving circuit includes n stages of second repeating units. Where m and n are positive integers, and 2≦m, 2≦n.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.