Patent · US Active

Masking method for semiconductor devices with high surface topography

US9466529B2 · kind B2 · utility

0Cited by
1References
11Claims
0Family size

Assignee

Inventors

Key dates

Filing dateJan 29, 2014
Grant dateOct 11, 2016
Priority date
Expiry dateJan 29, 2034

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH01L21/76898
  • WIPO fieldSemiconductors
  • WIPO sectorElectrical engineering

Abstract

The method comprises the steps of providing a semiconductor body or substrate (1) with a recess or trench (2) in a main surface (10), applying a mask (3) on the main surface, the mask covering the recess or trench, so that the walls and bottom of the recess or trench and the mask together enclose a cavity (4), which is filled with a gas, and forming at least one opening (5) in the mask at a distance from the recess or trench, the distance (6) being adapted to allow the gas to escape from the cavity via the opening when the gas pressure exceeds an external pressure.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.