Mechanism for MEMS bump side wall angle improvement
US9466541B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 21, 2015 |
| Grant date | Oct 11, 2016 |
| Priority date | — |
| Expiry date | Jan 21, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/1461
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present disclosure relates to a bump processing method and/or resulting MEMS-CMOS structure, in which one or more anti-stiction bumps are formed within a substrate prior to the formation of a cavity in which the one or more anti-stiction bumps reside. By forming the one or more anti-stiction bumps prior to a cavity, the sidewall angle and the top critical dimension (i.e., surface area) of the one or more anti-stiction bumps are reduced. The reduction in sidewall angle and critical dimension reduces stiction between a substrate and a moveable part of a MEMS device. By reducing the size of the anti-stiction bumps through a processing sequence change, lithographic problems such as reduction of the lithographic processing window and bump photoresist collapse are avoided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.