Packaged semiconductor device for high performance memory and logic
US9466561B2 · kind B2 · utility
3Cited by
9References
28Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jul 29, 2010 |
| Grant date | Oct 11, 2016 |
| Priority date | — |
| Expiry date | Jul 11, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3011
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A packaged semiconductor device is disclosed. The device comprises a substrate having multiple layers between first and second oppositely disposed faces, and a cavity with an opening at the first face to nest at least one integrated circuit memory device. Logic circuitry is disposed on the second face and includes contacts for electrically coupling to the stacked integrated circuit memory devices. The logic circuitry is coupled to electrical contacts formed on the first face through first electrical paths formed in the multiple layers of the substrate, the first electrical paths including conductive traces and vias.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.