Array substrates and optoelectronic devices
US9466621B2 · kind B2 · utility
8Cited by
4References
17Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jan 28, 2014 |
| Grant date | Oct 11, 2016 |
| Priority date | — |
| Expiry date | Jan 28, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/481
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
Disclosed is a method of forming array substrates having a peripheral wiring area and a display area. The method is processed by only three lithography processes with two multi-tone photomasks and one general photomask. In the peripheral wiring area, the top conductive line directly contacts the bottom conductive line without any other conductive layer. The conventional lift-off process is eliminated, thereby preventing a material (not dissolved by a stripper) from suspending in the stripper or remaining on the array substrate surface.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.