Manufacturing method for vertical channel gate-all-around MOSFET by epitaxy processes
US9466699B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 18, 2014 |
| Grant date | Oct 11, 2016 |
| Priority date | — |
| Expiry date | Jul 18, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/201
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A manufacturing method is provided for fabricating a vertical channel gate-all-around MOSFET by epitaxy processes. The method includes growing a first epitaxial layer on a top semiconducting layer of a substrate; etching the first epitaxial layer and the top layer to form a first source/drain pattern in the top layer; etching the first epitaxial layer to form a vertical channel structure; then forming a gate dielectric layer on the vertical channel structure surface; forming a sandwich structure composed of a bottom spacer layer, a gate electrode layer and a top spacer layer; etching the top spacer layer and the gate electrode layer to form a gate pattern followed by forming a top spacer structure thereon; growing a second epitaxial layer and etching to form a second source/drain pattern.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.