Semiconductor device and method of manufacturing the same

US9466705B2 · kind B2 · utility

Assignee

• Kabushiki Kaisha Toshiba · JP

Inventors

• Akira Yoshioka · Yokohama, JP
• Toru Sugiyama · Abiko, JP
• Yasunobu Saito · Tokyo, JP
• Kunio Tsuda · Ishikawa, JP

Key dates

• Filing date: Oct 6, 2015
• Grant date: Oct 11, 2016
• Expiry date: Oct 6, 2035

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D62/824

Abstract

A semiconductor device according to one embodiment includes an n-type first GaN-based semiconductor layer, a p-type second GaN-based semiconductor layer on the first GaN-based semiconductor layer. The second GaN-based semiconductor layer includes a low impurity concentration region and a high impurity concentration region. An n-type third GaN-based semiconductor layer is provided on the second GaN-based semiconductor layer. The device includes a gate electrode being located adjacent to the third GaN-based semiconductor layer, the low impurity concentration region, and the first GaN-based semiconductor layer intervening a gate insulating film. The device includes a first electrode on the third GaN-based semiconductor layer, a second electrode on the high impurity concentration region, and a third electrode on the opposite side of the first GaN-based semiconductor layer from the second GaN-based semiconductor layer.