Delay circuit
US9467131B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 10, 2015 |
| Grant date | Oct 11, 2016 |
| Priority date | — |
| Expiry date | Jun 10, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00019
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A delay circuit includes a current circuit, a first current mirror circuit, a second current mirror circuit, a self-compensation circuit, and a delay capacitor. A fixed ratio is between the first current and the second current provided by the current circuit. The first current mirror circuit generates a first mirror current in response to the first current. A partial current of the second current flowing through the second current mirror circuit is a base current, and the second current mirror circuit generates a second mirror current in response to the base current. The self-compensation circuit generates a feedback current in response to the second mirror current. The delay capacitor generates a delay signal. The charging current is equal to the second current subtracting the base current. The first mirror current is the sum of the base current, the second mirror current, and the feedback current.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.