Methods and systems for distributing clock and reset signals across an address macro
US9467149B2 · kind B2 · utility
2Cited by
4References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 31, 2014 |
| Grant date | Oct 11, 2016 |
| Priority date | — |
| Expiry date | Nov 4, 2034 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A distribution network for distributing clock and reset signals across an address macro has circuit blocks having dividers and counters, drivers connected in a balanced tree, and drivers connected in an unbalanced tree. The dividers and counters are synchronized relative to a clock signal. The drivers connected in the balanced tree distribute the clock signal synchronously to the circuit blocks. The drivers connected in the unbalanced tree distribute a reset signal to the circuit blocks. The clock signal is distributed via the balanced tree as a function of the reset signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.