Low power and compact area digital integrator for a digital phase detector
US9467153B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 20, 2015 |
| Grant date | Oct 11, 2016 |
| Priority date | — |
| Expiry date | Apr 20, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0807
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
In an example embodiment, a phase-locked loop circuit may include a first circuitry to receive a reference signal and a source signal. The first circuitry may generate a correction signal for demonstrating a difference in phase between the reference signal and the source signal. The phase-locked loop may include a second circuitry to receive the correction signal. The second circuitry may generate a digital signal for demonstrating a phase-to-digital conversion of the correction signal. The phase-locked loop may include a third circuitry to receive the digital signal. The third circuitry may generate a control signal for demonstrating a converted voltage of the digital signal. The phase-locked loop may include a fourth circuitry to receive the control signal. The fourth circuitry may generate the source signal in response to the control signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.