Restricting clock signal delivery in a processor

US9471088B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Alexander Gendler · Kiryat Motzkin, IL
• Efraim Rotem · Haifa, IL
• Julius Mandelblat · Haifa, IL
• Alexander Lyakhov · Haifa, IL
• Larisa Novakovsky · Haifa, IL
• George Leifman · Haifa, IL
• Lev Makovsky · Haifa, IL
• Ariel Sabba · Carmiel, IL
• Niv Tokman · Haifa, IL

Key dates

• Filing date: Jun 25, 2013
• Grant date: Oct 18, 2016
• Expiry date: Sep 22, 2034

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F1/32
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

In an embodiment, a processor includes a core to execute instructions, where the core includes a clock generation logic to receive and distribute a first clock signal to a plurality of units of the core, a restriction logic to receive a restriction command and to reduce delivery of the first clock signal to at least one of the plurality of units. The restriction logic may cause the first clock signal to be distributed to the plurality of units at a lower frequency than a frequency of the first clock signal. Other embodiments are described and claimed.