Microprocessor based power management system architecture
US9471121B2 · kind B2 · utility
7Cited by
4References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 14, 2012 |
| Grant date | Oct 18, 2016 |
| Priority date | — |
| Expiry date | May 14, 2034 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An electronic system is disposed on a single integrated circuit including a plurality of power domains and a power control manager. Each power domain may be independently powered. The power control manager includes a set of control registers storing individual control bits, a power switch for each power domain and a programmable microprocessor. The programmable microprocessor controls the digital state of individual bits within the control registers thereby controlling the ON and OFF state of the corresponding power domain.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.