Techniques for putting platform subsystems into a lower power state in parallel
US9471132B2 · kind B2 · utility
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5References
17Claims
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Key dates
| Filing date | Sep 27, 2013 |
| Grant date | Oct 18, 2016 |
| Priority date | — |
| Expiry date | Jun 10, 2034 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D30/50
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Various embodiments are generally directed to an apparatus, method and other techniques for determining a sleep configuration state for each of a plurality of subsystems having an associated subsystem sleep control register for entry into a lower power state, configuring each of the associated subsystem sleep control registers with the sleep configuration state for each of the subsystems and enabling the sleep configuration state for each of the subsystems in parallel when transitioning to the lower power state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.