Vectorized Galois field multiplication
US9471281B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 14, 2014 |
| Grant date | Oct 18, 2016 |
| Priority date | — |
| Expiry date | Jan 20, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2207/72
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments relate to vectorized Galois field multiplication. An aspect includes a subdivision of first and second input operands into vector elements of equal sizes with multiple modes defined such that a base mode has a size corresponding to a smallest vector element size, which is a factor of a size of the first and second input operands, and a higher mode has a size that is a multiple of the base mode size. The vector elements of the first input operand are modified with a bit mask based on a size of the vector elements. The modified vector elements of the first input operand and the vector elements of the second input operand are input into a single hardware tree configured for subdivision into staggered subtrees a size of each of which being based on the base mode size.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.