System and processor that include an implementation of decoupled pipelines
US9471307B2 · kind B2 · utility
8Cited by
3References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 3, 2014 |
| Grant date | Oct 18, 2016 |
| Priority date | — |
| Expiry date | Jun 24, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3873
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and apparatus are provided that include an implementation for decoupled pipelines. The apparatus includes a scheduler configured to issue instructions to one or more functional units and a functional unit coupled to a queue having a number of slots for storing instructions. The instructions issued to the functional unit are stored in the queue until the functional unit is available to process the instructions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.