Memory system that detects bit errors due to read disturbance and methods thereof
US9471418B2 · kind B2 · utility
6Cited by
25References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 23, 2012 |
| Grant date | Oct 18, 2016 |
| Priority date | — |
| Expiry date | Mar 28, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/13
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Methods and memory systems are provided that can detect bit errors due to read disturbances. A main page of a flash memory in a memory system is read. A bit error in data that is read from the main page is detected and corrected. In parallel with reading the main page, a bit error is detected in data that is read from a dummy page of the flash memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.