Gate driver circuit basing on IGZO process
US9472155B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 19, 2014 |
| Grant date | Oct 18, 2016 |
| Priority date | — |
| Expiry date | Dec 13, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2310/0286
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
The present invention provides a gate driver basing on IGZO process, comprising: GOAs in cascade connection comprising a Nth-stage GOA, wherein the Nth-stage GOA further comprising: a pull-up control part 100, a pull-up part 200, a transfer part 300, a pull-down part 400, a pull-down holding part 500, a boost part 600, a first negative supply VSS1, a second negative supply VSS2, a third negative supply VSS3, which are three gradually decreasing negative supplies and pull down an output terminal G(N), a first node Q(N), a second node P(N), and a driving single ST(N) to prevent the electrical leakage of TFTs effectively. And channels of the TFT switches of the gate driver basing on the IGZO process are oxide semiconductor channels.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.