Mitigating parasitic current while programming a floating gate memory array
US9472288B2 · kind B2 · utility
12Cited by
8References
15Claims
0Family size
Assignee
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Key dates
| Filing date | Oct 29, 2014 |
| Grant date | Oct 18, 2016 |
| Priority date | — |
| Expiry date | Oct 29, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG03G21/1882
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods to program a floating gate memory array include, in response to a request to program a second bit of the floating gate memory array, at a first time, outputting a programming voltage to cause a first node voltage at a first source of a first transistor corresponding to a first bit, wherein the first node voltage is greater than a second node voltage at a second source of a second transistor corresponding to the second bit. The method further includes at a second time, increasing the programming voltage of the floating gate memory array to program the second bit of the floating gate memory array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.