Apparatus and methods for high-density chip connectivity
US9472529B2 · kind B2 · utility
5Cited by
1References
1Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jun 11, 2015 |
| Grant date | Oct 18, 2016 |
| Priority date | — |
| Expiry date | Jun 11, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/117
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An electronic circuit and method may include a first chip including first electronics and a first connector including multiple self-alignment features and conductive pads. A second chip may include second electronics and a second connector including multiple self-alignment features and conductive pads. The first chip and second chip may be indirectly horizontally aligned with one another and in electrical communication with one another via the first and second connectors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.