Semiconductor arrangement with electrostatic discharge (ESD) protection
US9472545B2 · kind B2 · utility
2Cited by
5References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 31, 2014 |
| Grant date | Oct 18, 2016 |
| Priority date | — |
| Expiry date | Jan 31, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
One or more semiconductor arrangements having a stacked configuration and electrostatic discharge (ESD) protection are provided. The semiconductor arrangements include a first substrate, a second substrate, an ESD pad, an ESD device and a first interlayer via connecting the first substrate and the second substrate. The first substrate includes a first PMOS device and a first device and the second substrate includes a first NMOS device and a second device. Alternatively, the first substrate includes a first PMOS device and a first NMOS device and the second substrate includes a first device and a second device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.