Array substrate with improved pad region
US9472579B2 · kind B2 · utility
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8Claims
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Key dates
| Filing date | Oct 9, 2014 |
| Grant date | Oct 18, 2016 |
| Priority date | — |
| Expiry date | Oct 9, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10H20/817
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
An array substrate having a wiring of a pad region formed without an insulating film or without an insulating film and an organic film to reduce abnormal operations due to an increase in resistance caused by a contact margin at a high temperature, and a method for manufacturing the same are provided. The array substrate includes: an insulating substrate including a pad region and a thin film transistor (TFT) formation region; a first electrode layer formed in the pad region of the substrate; and a second electrode formed on the first electrode layer in an overlapping manner.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.