Power management with flip-flops
US9473113B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 24, 2015 |
| Grant date | Oct 18, 2016 |
| Priority date | — |
| Expiry date | Sep 24, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/35625
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An integrated circuit (IC) is disclosed herein for managing power with flip-flops having a retention feature. In an example aspect, an IC includes a constant power rail, a collapsible power rail, multiple flip-flops, and power management circuitry. Each flip-flop of the multiple flip-flops includes a master portion that is coupled to the collapsible power rail and a slave portion that is coupled to the constant power rail. The power management circuitry is configured to combine a clock signal and a retention signal into a combined control signal and to provide the combined control signal to each flip-flop of the multiple flip-flops.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.