Substrate and method for manufacturing semiconductor package
US9474145B2 · kind B2 · utility
3Cited by
23References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 2, 2015 |
| Grant date | Oct 18, 2016 |
| Priority date | — |
| Expiry date | Jun 2, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2201/0909
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A substrate for a semiconductor package and a method for manufacturing a semiconductor package are disclosed. The substrate comprises a surface, and package unit regions arranged on the surface in a row direction to form a plurality of rows. The package unit regions of an n+1-th row are arranged offset in a row direction from the package unit regions of an n-th row. The method includes molding semiconductor chips and spaces between the substrate and the semiconductor chips on the package unit regions of the last row at substantially the same time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.