Source driver with reduced number of latch devices
US9477104B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 23, 2014 |
| Grant date | Oct 25, 2016 |
| Priority date | — |
| Expiry date | Jun 23, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2330/021
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A source driver with reduced number of latch devices includes a master latch device and at least one slave latch device. The master latch device has a first transmission gate, a first inverter, a second inverter, a first enable gate, and a second enable gate. The output of the second inverter is connected to the input of the first inverter. The at least one slave latch device has a second transmission gate, a third inverter, and a fourth inverter. When the first enable gate and the second enable gate receive a latch enable signal and a complementary latch enable signal respectively, the master latch device and the at least one slave latch device are concurrently driven to latch data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.